东芝元器件
PRODUCTS CENTER
High-Performance SoC Design
Challenges of Large-Scale and High-Performance SoCs
For the development of a large-scale SoC, it is important to reduce not only the die area but also power consumption and implementation turnaround time. High-performance SoCs require clock tree and other implementation techniques, as well as a full complement of power integrity (PI), signal integrity (SI) and thermal solutions.
Power, Performance and Area (PPA) Optimization
- Optimized cell libraries
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Toshiba provides you with cell libraries specifically optimized for your design to help reduce die area and power consumption.
- Reducing overhead by optimizing design sign-off conditions
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Toshiba helps reduce area overhead and turnaround time (TAT) for timing closure by optimizing the sign-off conditions of a design according to its specification.
- Implementation without design iteration using a floorplan evaluation system
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Our floorplan evaluation system provides an objective indication of your floorplan quality to eliminate the need for trial-and-error adjustment and thus prevent delays in a development project.
Solutions for High-Performance SoCs
- PLL and high-performance clock tree technologies necessary for high-speed operation
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Drawing on extensive experience with implementation, Toshiba achieves a high-speed design using low-jitter PLLs, clock trees with a good balance of power and skew, and other techniques.
- Feedback to the product specification and design from early power integrity (PI), signal integrity (SI) and thermal analyses
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PI, SI and thermal issues become significant challenges in realizing high-performance SoCs. By using advanced modeling, simulation and analysis technologies, the results of PI, SI and thermal analyses are fed back to a design at an early stage in order to achieve working hardware.
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